Method and apparatus for improvements in chip manufacture and design

ABSTRACT

A method of securing a bond pad in to a semiconductor chip having an upper top metal surface which includes one or more holes, the method comprising the steps of forming a passivation layer over the upper metal surface, which passivation layer has holes therein substantially corresponding to the or each hole in the upper metal layer and being substantially the same size or smaller than the holes in the upper metal layer; forming the bond pad over the passivation layer; characterised in that the step of forming the bond pad comprises introducing some of the material from the bond pad into the holes in the passivation layer and upper metal layer when forming the bond pad, securing the bond pad to the passivation layer by allowing said material to flow under the surface thereof and attach thereto without attaching to the upper metal layer to thereby form a securing means.

FIELD OF THE INVENTION

This invention relates to a method and apparatus for improving chipmanufacture and design, particularly but not exclusively in respect ofincreased robustness and anchoring for bond pad or bumps in metallayers.

BACKGROUND OF THE INVENTION

The technology of chips continues to change and generally this means afurther reduction in size. Each reduction in size presents more problemswhich must be overcome. In particular for smaller devices one of themain issues which arise is the strength or robustness of the chips. Thisis the case in all parts of the chip but can be more of an issue in theareas where probing or other types of testing are carried out.

The problems of spreading the forces of testing have been discussed in anumber of documents with respect to the domain of micro technology (i.e.size ˜10⁻⁶ m). For example U.S. Pat. No. 6,563,226 B2 (Motorola) andU.S. Pat. No. 6,717,270 (Motorola) describe the use ofprobe-over-passivation (POP); bond-over-passivation (BOP) and bond overactivated layer (BOA) processes.

US 200005/0121803 A1 relates to an internally reinforced bond pad. Thereinforced bond pad has a non planar dielectric structure and a metallicbond layer which conforms with this non-planar dielectric structure.This invention requires a dual inlaid bonding surface (which needs avery complex process with many steps). U.S. Pat. No. 6,531,384 B1discloses a so called “armoured” bond pad. This patent teaches astructure having a number of islands of copper metal 18 extending abovethe insulation 14. In addition this patent deals with bonding andprobing in the same area. The metal dielectric pattern is an uppermostmetal e.g. aluminium and would not be compatible with fine-pitch bondpads. This also limits bond over activation (BOA) compatibility becausethe bonding surface must be electrically connected by underlying metallayers. The alternation of copper islands and passivation providesvertical connectivity. To make this alternation of copper islands andpassivation layer requires a number of additional steps of processingwhich add to the cost and time for making the device.

SUMMARY OF THE INVENTION

The present invention provides a method and apparatus as described inthe accompanying claims.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional diagram of the first embodiment of a chip,in accordance with one embodiment of the present invention;

FIG. 2 is a detailed section of the layers in the region of thepassivation layer shown in FIG. 1, in accordance with one embodiment ofthe present invention;

FIG. 3 is a diagram showing a plan view of the passivation layer inaccordance with one embodiment of the present invention; and

FIG. 4 is a flow chart showing method steps in accordance with oneembodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring to FIG. 1, a nanometre technology active device is shown 100.The device could be produced on a silicon base and be something such asa MOSFET, a diode, etc. The silicon layer is shown as 102. The device ismade up of a plurality of layers of metal and insulator 104, formed withvias and other connections 106 there-between as appropriate. The natureand design of the layers would be dependant on the specific nature ofthe device. The layers of metal would typically be of copper or anyother appropriate metal and the layers of insulator would be of anydielectric material as is appropriate to the process and devicerequired. The uppermost metal layer 108 is formed in accordance with thefinal design of the chip. Then a passivation layer 110 is applied overthe surface of the chip and patterned as appropriate to allow bonding tooccur in a wire bond region 112. The patterning of the passivation layeris similar to that of the upper metal layer 108, in order that there areholes therein which substantially correspond with any holes in the metallayer. The reason for these holes will be described in greater detailbelow. Two such holes are labelled as 114 and 116 in the region of theprobe area 118. A bond pad layer (aluminium layer) 120 is applied and,in the surface of the probe area or probe region 118, a number ofpassivation vias 122 are patterned. The bond pad layer 120 could be ofcopper, aluminium or any other appropriate material and may not coverthe complete surface of the device, being instead at various areas orregions. The function of the passivation vias 122 are described ingreater detail in our co-pending application SC14021CF filed on commondate herewith and incorporated herein by reference.

The probe 124 makes contact with the probing region and a force isapplied. Due to the fact that the vias exist underneath the probe, notall the stress of the probing is concentrated on one particular point;in fact the maximum stress of the probe is spread over all the areasaround the vias. The patterned vias on the probe over passivation spaceeffectively distribute the stress of probing. After the probing processhas been carried out and the chip has passed the necessary test, thewire bond 126 may then be attached to the wire bond region 112.

The vias may patterned over both the probe and wire bond regions. Thiscan be useful if any tests are carried out over the wire bond region orbump region (region for bumping). Also the pattering is the same for thewhole of layer 120 which means a less complex fabrication process may beadopted.

The passivation vias can be shaped in any manner, for example, squareshoneycomb, circular etc. The shape and size of the holes are configuredin such a way that the hole is smaller than the probe tip and so thatthe tip cannot catch on the edge of the hole. The holes may have forexample chamfered or similar edges. In addition, if the general designrequirements set out above are met for different shapes of hole, thereis no limit to the shape, orientation, number etc of the vias.

Referring now to FIG. 2 a more detailed drawing of the region of thepassivation layer is shown. The area shown includes the uppermost layerof the chip 108 with the passivation layer 110 thereon. The holes in thepassivation layer 114 and 116 are also shown in more detail. Thepassivation layer 110 slightly overlies the metal layer 108 to providean overhanging region 200. When the bond pad layer 120 is applied someof the metal seeps into the holes and extends along some of the lengthof the overhanging region to give rise to an anchor 202. The anchoreffectively “hooks” around the edges of the hole forming an attachmentthereto as the metal solidifies. It will be appreciated that the anchoror anchor point can be formed in any other appropriate way and theinvention is not limited to them being formed by the flow of moltenmetal and the solidification thereof.

The uppermost metal layer of the chip 300 is shown from above in FIG. 3.The top surface includes a plurality of holes 302 in the form of a gridshown generally at 304. In the figure the grid does not extent over thewhole surface of the top metal layer, but it could if circumstancesdictated this requirement. In addition the layer may be a number ofregions instead of a layer. The holes are shown as square holes, butthis again does not need to be the case. The holes can be any shape andsize. On application of the passivation layer the grid format of the topmetal layer is preserved such that the holes are still evident fromabove. The holes will be slightly smaller due to the existence of theoverhanging region that is formed by the passivation layer. Thus whenthe bond pad is applied the molten metal enters each of the holes 302and forms an anchor therein.

The term anchor is used as the term for the metal plug which is formedin the hole and which extends into the region of the overhanging region.However, it will be appreciated that the anchor may take many differentshapes and forms. The term anchor includes any other type of fastening,securing or connecting means which has the same function, i.e. that ofadding an additional element of attachment of the bond pad layer to thepassivation layer.

The size of the overhang region must be carefully determined so that themetal of the anchor does not make contact with the uppermost metal layer108 and cause short circuits and the like. The determination may dependon the types of metal used; the flowability of the metal; the size ofthe hole and the overhangs; the nature of the materials of all thelayers and/or other details of the chip design and size. The minimumdistance between the anchor and the metal layer 108 depends on thedesign rules applied for the considered technology to avoid anyelectrical problems in the final chip.

The aluminium layer 120 is one example of a layer on the chip wherebonding or probing might occur. There may be other types of layer inother circumstances where the anchor points are also applicable anduseful. For example, layers of different metals at different places onthe chip. All that is required is that there is an upper layer orregions over the passivation layer which have been formed to give risethe anchor point described above.

The addition of the anchor point provides improved bond pad reliabilityfor the bond pad layer. This can be demonstrated in for example peelingtests. The results of such peeling tests give rise to 100% success ratefor chips tested, that are formed with an anchor in accordance with anembodiment of the present invention.

Due to the anchor and the manner in which this is formed the last metallayer under the POP or bond pad is free to be used for routing whichopens up more functionality for a device in accordance with anembodiment of the present invention. In addition, the mechanicalcapabilities of the bond pad are considerably augmented as compared withthe same type of chip without the benefits of an embodiment of thepresent invention. Additionally the bond pad of an embodiment of thepresent invention offers a reduced risk of cracking during probing andbond application, which thus enables use of a larger process window.

As previously indicated there are a number of passivation vias 122 whichmay be included in the upper surface of the bond pad layer 120. Thesevias increase the stresses that the surface of the device can sustainwhen a probing test is carried out as described in our co-pendingapplication SC14021CF. As can been seen in FIG. 2 the vias 122 and theholes 114 and 116 may be aligned. In other words the passivation viasare located above or partially above the holes. If this is the casethere is a still greater strength and robustness in the chipparticularly during any probing or bonding operations or in general forany assembly and test operations.

The steps of manufacturing any chip which includes an anchor such asthat described above will now be described with reference to FIG. 4. Thechip is manufactured in the normal way, depending on the chip design andrequirements (Step 400). The uppermost or top metal layer of the chip isapplied (Step 402). This step can be carried out by any appropriateprocess. The uppermost metal layer includes a number of holes (which aresometimes called donuts) over the surface thereof. The passivation layeris then formed such that the holes are preserved in any area where bondpad anchoring is required (Step 404). The bond pad layer or regions arethen applied (step 406). The passivation and bond pad may be fabricatedby any appropriate processing method.

It will be appreciated that variations of the present invention arepossible in respect of the elements and examples presented therein andthat these variations are hereby included herein.

1. A method of securing a bond pad to a semiconductor chip having anupper metal layer which includes one or more holes, the methodcomprising the steps of: forming a passivation layer over the uppermetal layer, wherein the passivation layer has one or more holestherein, that overlies one or more holes in the upper metal layer andare substantially the same size or smaller than the one or more holes inthe upper metal layer; forming the bond pad over the passivation layer;wherein forming the bond pad comprises introducing some of the materialfrom the bond pad into the one or more holes in the passivation layerand upper metal layer when forming the bond pad, and allowing portionsof the material of the bond pad to flow under the surface of thepassivation layer and attach thereto without attaching to the uppermetal layer to secure the bond pad to the passivation layer.
 2. Themethod of claim 1 wherein the step of introducing the material comprisesapplying molten material onto the passivation layer such that moltenmaterial enters the one or more holes and flows along the underside ofthe passivation layer.
 3. The method of claim 2, wherein the step offorming the passivation layer comprises forming the passivation layerhaving the one or more holes which are smaller than the one or moreholes in the metal layer.
 4. The method of claim 2, further comprisingforming the one or more holes to be substantially rectilinear.
 5. Themethod of claim 2, further comprising forming the one or more holes tobe substantially circular.
 6. The method of claim 1, wherein the step offorming the passivation layer comprises forming the passivation layerhaving holes which are smaller than the one or more holes in the metallayer.
 7. The method of claim 1, further comprising forming the one ormore holes to be substantially rectilinear.
 8. The method of claim 1,further comprising forming the one or more holes to be substantiallycircular.
 9. The method of claim 1, wherein the step of forming thepassivation layer comprises forming the passivation layer having the oneor more holes which are smaller than the one or more holes in the metallayer.
 10. The method of claim 1, further comprising forming the one ormore holes to be substantially rectilinear.
 11. The method of claim 1,further comprising forming the one or more holes to be substantiallycircular.
 12. A semiconductor chip having an upper metal layer whichincludes one or more holes, the chip further comprising: a passivationlayer over the upper metal layer, wherein the passivation layer has oneor more holes therein that overlies one or more holes of the upper metallayer and substantially the same size or smaller than the one or moreholes of the upper metal layer; and a bond pad formed over thepassivation layer; wherein the bond pad comprises a material thatextends through the one or more holes in the passivation layer and uppermetal layer wherein portions of the material extend along an undersideof the passivation layer without attaching to the upper metal layer tosecure the bond pad to the passivation layer.
 13. The semiconductor chipof claim 12, wherein the one or more holes in the passivation layer aresmaller than the one or more holes in the upper metal layer.
 14. Thesemiconductor chip of claim 13, wherein the one or more holes issubstantially rectilinear.
 15. The semiconductor chip of claim 13,wherein the one or more holes is substantially circular.
 16. Thesemiconductor chip of claim 12, wherein the one or more holes issubstantially rectilinear.
 17. The semiconductor chip of claim 12,wherein the one or more holes is substantially circular.
 18. Thesemiconductor chip of claim 12, wherein the material is a moltenmaterial which enters the one or more holes and flows along theunderside of the passivation layer.